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11	This document is scheduled to be published in the Federal Register onand available online at http://federalregister.gov/a, and on FDsys.gov LIBRARY OF CONGRESS U.S. Copyright Office Add to Reading List Source URL: copyright.gov Language: English - Date: 2015-10-27 10:37:52 Hardware restrictions Law 105th United States Congress Digital Millennium Copyright Act Copyright law Unlocking Consumer Choice and Wireless Competition Act Anti-circumvention Copyright Notice of proposed rulemaking Register of Copyrights United States Copyright Office FAIR USE Act
12	This document is scheduled to be published in the Federal Register onand available online at http://federalregister.gov/a, and on FDsys.gov LIBRARY OF CONGRESS U.S. Copyright Office Add to Reading List Source URL: www.copyright.gov Language: English - Date: 2015-10-27 10:37:52 Law Hardware restrictions 105th United States Congress United States administrative law Digital Millennium Copyright Act Copyright law Unlocking Consumer Choice and Wireless Competition Act Anti-circumvention Notice of proposed rulemaking Copyright law of the United States Copyright Register of Copyrights
13	Decim, a new stream cipher for hardware applications ∗ C. Berbain1 , O. Billet1 , A. Canteaut2 , N. Courtois3 , B. Debraize3,4 , H. Gilbert1 , L. Goubin4 , A. Gouget5 , L. Granboulan6 , C. Lauradoux2 , M. Minier2 , T. Add to Reading List Source URL: www.rocq.inria.fr Language: English - Date: 2006-03-23 04:05:33 Cryptography Stream ciphers Pseudorandom number generators Linear-feedback shift register Correlation attack Self-shrinking generator Grain QUAD Turing Shrinking generator Shift register
14	Appears in the Proceedings of 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’12) Architecture Support for Disciplined Approximate Programming Hadi Esmaeil Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2012-01-11 16:58:46 Computer engineering Instruction set architectures Microarchitecture Microprocessors Register file Instruction set DEC Alpha CPU cache Cell Computer architecture Computer hardware Central processing unit
15	TMS9927 and TMS9937 Single-Chip Video Timers/Controllers Data Manual IMPORTANT NOTICES Add to Reading List Source URL: bitsavers.informatik.uni-stuttgart.de Language: English - Date: 2015-01-14 16:01:14 Electronics Central processing unit Processor register Raster scan Texas Instruments TMS9900 Motorola MOS Technology Graphics chips Computer hardware Electronic engineering
16	Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches Alen Bardizbanyan† , Magnus Sj¨alander‡ , David Whalley‡ , and Per Larsson-Edefors† † Chalmers University of Technology, Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2013-11-15 06:28:01 Computer memory Cache CPU cache Translation lookaside buffer Lookup table Processor register Sum addressed decoder R8000 Computer hardware Central processing unit Computing
17	The Elements of Computing Systems Add to Reading List Source URL: nand2tetris.org Language: English - Date: 2012-07-23 06:35:44 Central processing unit Classes of computers Digital electronics Instruction cycle Memory-mapped I/O Instruction set Computer Machine code Processor register Computer hardware Computer architecture Computing
18	5th Generation Intel® Core™ Processor Family, Intel® Core™ M Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family Add to Reading List Source URL: www.intel.com.tr Language: English - Date: 2015-06-11 08:09:31 X86 architecture Intel Celeron Direct Media Interface X86 virtualization Control register X86-64 Centrino Computer hardware Computing Computer architecture
19	Operating Systems: Internals and Design Principles Add to Reading List Source URL: homepage.smc.edu Language: English - Date: 2015-03-13 20:59:11 Central processing unit Memory buffer register Instruction set Microprocessor Instruction cycle Datapath Computer hardware Computer architecture Computing
20	Designing with VHDL FPGA 1 LANG11000-ILT (v1.0) Course Specification Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2014-11-12 18:34:24 VHDL Digital electronics Field-programmable gate array Logic synthesis Xilinx Register-transfer level Electronic engineering Hardware description languages Electronic design automation

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